As the density of semiconductor devices increases, the demands on interconnect layers for connecting the semiconductor devices to each other also increase. Therefore, there is a desire to switch from the traditional aluminum metal interconnects to copper interconnects. Unfortunately, suitable copper etches for a semiconductor fabrication environment are not readily available. To overcome the copper etch problem, damascene processes have been developed.
In a conventional interconnect process, the aluminum (and any barrier metals) are deposited, patterned, and etched to form the interconnect lines. Then, an interlevel dielectric (ILD) is deposited and planarized. In a damascene process, the ILD is formed first. The ILD is then patterned and etched. The metal is then deposited over the structure and then chemically-mechanically polished to remove the metal from over the ILD, leaving metal interconnect lines. A metal etch is thereby avoided.
One prior art damascene process, a dual damascene process, is described with reference to FIGS. 1A-E. Referring to FIG. 1A, a silicon nitride layer 12 is deposited over a semiconductor body 10. Semiconductor body 10 will have been processed through a first metal interconnect layer. A via level dielectric 14 is deposited over silicon nitride layer 12. Via dielectric layer 14 comprises FSG (fluorine-doped silicate glass). Another silicon nitride layer 18 is deposited over via level dielectric 14 and a second, trench level dielectric 20 is deposited over silicon nitride layer 18. A via 22 is then patterned and etched through the trench level dielectric 20, silicon nitride layer 18 and via level dielectric 14. Silicon nitride layer 12 is used as a via etch-stop.
Referring to FIG. 1B, a spin-on organic BARC (bottom anti-reflection coating) 24 is deposited to fill a portion of via 22. The result is approximately 600 Å of BARC over dielectric 20 and a thickness of ˜2000-2500 Å inside the via 22. BARC 24 protects via 22 during the subsequent trench etch. Next, the trench pattern 26 is formed on the structure as shown in FIG. 1C. Trench pattern 26 exposes areas of trench level dielectric 20 (with about 600 Å of BARC on top of dielectric 20) where the metal interconnect lines are desired. Referring to FIG. 1D, the trench etch to remove portions of FSG layer 20 is performed. Oxide ridges 28 may undesirably form on the edges of via 22. Pattern 26 is removed as shown in FIG. 1E. Oxide ridges impair device reliability due to the fact that it is difficult to ensure that a metal barrier completely covers the oxide ridges.
Newer technologies are switching to even lower-k dielectrics such as organo-silicate glass (OSG) or ultra-low-k films in place of FSG. Dual damascene processes for working with the newer dielectrics are needed.